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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad743 ultralow noise bifet op amp features ultralow noise performance 2.9 nv/ hz at 10 khz 0.38 v p-p, 0.1 hz to 10 hz 6.9 fa/ hz current noise at 1 khz excellent dc performance 0.5 mv max offset voltage 250 pa max input bias current 1000 v/mv min open-loop gain ac performance 2.8 v/ s slew rate 4.5 mhz unity-gain bandwidth thd = 0.0003% @ 1 khz available in tape and reel in accordance with eia-481a standard applications sonar preamplifiers high dynamic range filters (>140 db) photodiode and ir detector amplifiers accelerometers connection diagrams 8-lead pdip (n) 16-lead soic (r) ad743 8 top view top view 1 2 3 7 6 8 5 4 out null nc +v s +v s nc = no connect nc = no connect ad743 8 1 2 3 4 nc nc nc output nc nc 8 7 6 5 9 10 11 12 13 14 16 15 ?v s ?in +in nc offset null offset null nc nc nc null ?in +in ?v s general description the ad743 is an ultralow noise, precision, fet input, monolithic operational amplifier. it offers a combination of the ultralow volt- age noise generally associated with bipolar input op amps and the very low input current of a fet input device. furthermore, the ad743 does not exhibit an output phase reversal when the negative common-mode voltage limit is exceeded. the ad743? guaranteed, maximum input voltage noise of 4.0 nv/ hz at 10 khz is unsurpassed for a fet input mono- lithic op amp, as is the maximum 1.0 v p-p, 0.1 hz to 10 hz noise. the ad743 also has excellent dc performance with 250 pa maximum input bias current and 0.5 mv maximum offset voltage. the ad743 is specifically designed for use as a preamp in capaci- tive sensors, such as ceramic hydrophones. the ad743j is rated over the commercial temperature range of 0 c to 70 c. the ad743 is available in a 16-lead soic and 8-lead pdip. product highlights 1. the low offset voltage and low input offset voltage drift of the ad743 coupled with its ultralow noise performance mean that the ad743 can be used for upgrading many applications now using bipolar amplifiers. 2. the combination of low voltage and low current noise make the ad743 ideal for charge sensitive applications such as accelerometers and hydrophones. 3. the low input offset voltage and low noise level of the ad743 provide >140 db dynamic range. 4. the typical 10 khz noise level of 2.9 nv/ hz permits a three op amp instrumentation amplifier, using three ad743s, to be built which exhibits less than 4.2 nv/ hz noise at 10 khz and which has low input bias currents. 100 1k 10k 100k 1 10 100 1000 1m 10m source resistance ( ) op27 and resistor ad743 and resistor resistor noise only ad743 and resistor or op27 and resistor ( ) (? ? ?) ( ? ) r source r source o e in p u t v o lta g e n o is e (nv / h z ) figure 1. input voltage noise vs. source resistance
rev. e e2e ad743especifications (@ 25 c and 15 v dc, unless otherwise noted.) parameter conditions min typ max unit input offset voltage 1 initial offset 0.25 1.0 mv initial offset t min to t max 1.5 mv vs. temperature t min to t max 2 v/ c vs. supply (psrr) 12 v to 18 v 2 90 96 db vs. supply (psrr) t min to t max 88 db input bias current 3 either input v cm = 0 v 150 400 pa either input @ t max v cm = 0 v 8.8 na either input v cm = 10 v 250 600 pa either input, v s = 5 v v cm = 0 v 30 200 pa input offset current v cm = 0 v 40 150 pa offset current @ t max v cm = 0 v 2.2 na frequency response gain bw, small signal g = e1 4.5 mhz full power response v o = 20 v p-p 25 khz slew rate, unity gain g = e1 2.8 v/ s settling time to 0.01% 6 s total harmonic distortion 4 f = 1 khz (tpc 16) g = e1 0.0003 % input impedance differential 1 20 pf common mode 3 18 pf input voltage range differential 5 20 v common-mode voltage +13.3, e10.7 v over maximum operating range 6 e10 +12 v common-mode rejection ratio v cm = 10 v 80 95 db t min to t max 78 db input voltage noise 0.1 hz to 10 hz 0.38 v p-p f = 10 hz 5.5 nv/ hz f = 100 hz 3.6 nv/ hz f = 1 khz 3.2 5.0 nv/ hz f = 10 khz 2.9 4.0 nv/ hz input current noise f = 1 khz 6.9 fa/ hz open-loop gain v o = 10 v, r load 2 k 1000 4000 v/mv t min to t max 800 v/mv r load = 600 1200 v/mv output characteristics voltage r load 600 +13, e12 v r load 600 +13.6, e12.6 v t min to t max +12, e10 v r load 2 k 12 +13.8, e13.1 v current short circuit 20 40 ma power supply rated performance 15 v operating range 4.8 18 v quiescent current 8.1 10.0 ma transistor count no. of transistors 50 notes 1 input offset voltage specifications are guaranteed after five minutes of operation at t a = 25 c. 2 test conditions: +v s = 15 v, ev s = 12 v to 18 v; and +v s = 12 v to 18 v, ev s = 15 v. 3 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = 25 c. for higher temperature, the current doubles every 10 c. 4 gain = e1, r l = 2 k , c l = 10 pf. 5 defined as voltage between inputs, such that neither exceeds 10 v from common. 6 the ad743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded. all min and max specifications are guaranteed. specifications subject to change without notice.
rev. e ad743 e3e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad743 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and ev s storage temperature range (n, r) . . . . . . . e65 c to +125 c operating temperature range ad743j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to 70 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-lead pdip:
rev. e e4e ad743etypical performance characteristics 20 15 10 0510 supply voltage ( v) input voltage swing (v) 15 2 0 5 0 r load = 10k +v in ?v in tpc 1. input voltage swing vs. supply voltage 12 9 6 0510 supply voltage ( v ) quiescent current (ma) 15 20 3 0 tpc 4. quiescent current vs. supply voltage 300 200 ?12 ?9 3 6 9 12 ?6 common-mode voltage (v) input bias current (pa) ?3 0 100 0 tpc 7. input bias current vs. common-mode voltage (@ 25 c, v s = 15 v) 20 15 10 0510 supply voltage ( v) output voltage swing (v) 15 20 50 0 r load = 10k negative supply positive supply tpc 2. output voltage swing vs. supply voltage temperature ( c) input bias current (a) ?60 ?40 ?20 0 20 40 60 80 100 120 140 10 ?12 10 ?11 10 ?10 10 ?9 10 ?8 10 ?7 10 ?6 tpc 5. input bias current vs. temperature temperature ( c) current limit (ma) ?60 ?40 ?20 0 20 40 60 80 100 120 14 0 0 10 20 30 40 50 60 70 80 ? output current + output current tpc 8. short circuit current limit vs. temperature 20 25 30 35 15 10 10 100 1k load resistance ( ) output voltage swing (v p-p) 10 k 5 0 tpc 3. output voltage swing vs. load resistance 1 10 100 200 0.1 10k 100k 1m frequency ( hz ) output impedance ( ) 10m 100m 0.01 tpc 6. output impedance vs. frequency (closed-loop gain = e1) temperature ( c) gain bandwidth product (mhz) ?60 ?40 ?20 0 20 40 60 80 100 120 14 0 2.0 3.0 4.0 5.0 6.0 7.0 tpc 9. gain bandwidth product vs. temperature
rev. e ad743 e5e 20 40 60 80 100 0 0 100 1k 10k 100k frequency (hz) open-loop gain (db) phase margin (degrees) 1m 10m 100m ?20 20 40 60 80 100 ?20 phase gain tpc 10. open-loop gain and phase vs. frequency 40 60 80 100 120 20 100 1k 10k frequency (hz) common-mode rejection (db) 100k 1m 0 v cm = 10v tpc 13. common-mode rejection vs. frequency ?100 ?90 ?80 ?70 ?110 10 100 1k frequency (hz) thd (db) 10k 100 k ?140 ?130 ?120 gain = +10 gain = ?1 tpc 16. total harmonic distortion vs. frequency temperature ( c) slew rate (v/ s) ?60 ?40 ?20 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 tpc 11. slew rate vs. temperature (gain = e1) 20 40 60 80 100 120 100 1k 10k 100k frequency (hz) power supply rejection (db) 1m 10m 100m 0 + supply ? supply tpc 14. power supply rejection vs. frequency 1 10 100 frequency (hz) voltage noise (preferred to input) (nv/ hz ) 0.1 closed-loop gain = 1 closed-loop gain = 10 11 0 100 1k 10k 100k 1m 10m tpc 17. input voltage noise spectral density 140 150 130 120 0510 supply voltage ( v) open-loop gain (db) 15 20 100 80 tpc 12. open-loop gain vs. supply voltage, r load = 2 k 20 25 30 35 15 10 10 100 1k frequency (hz) output voltage (v p-p) 10 k 5 0 r l = 2k tpc 15. large signal frequency response 10 100 1k 110 100 1k frequency (hz) current noise spectral density (fa/ hz ) 10k 100 k 1 tpc 18. input current noise spectral density
rev. e e6e ad743 2.5 3 9 15 21 27 33 39 45 51 57 63 69 2.7 2.9 3.1 3.3 3.5 3.8 number of units input voltage noise (nv/ hz ) tpc 19. typical noise distribution @ 10 khz (602 units) +v s ad743 adjust 0.1 f 0.1 f 1 4 2 7 5 6 3 1 f 1m 2m 1 f ?v s v os tpc 20. offset null configuration +v s v out v in ad743 * optional, not required square wave input 0.1 f 0.1 f 4 2 7 6 3 * 1 f c l 10pf r l 2k 300 1 f ?v s tpc 21. unity-gain follower tpc 22. unity-gain follower large signal pulse response tpc 23. unity-gain follower small signal pulse response +v s v out v in ad743 square wave input 0.1 f 0.1 f 4 2 7 6 3 1 f c l 100pf 2k 2k 100pf 1 f ?v s tpc 24. unity-gain inverter tpc 25. unity-gain inverter large signal pulse response tpc 26. unity-gain inverter small signal pulse response
rev. e ad743 e7e op amp performance: jfet vs. bipolar the ad743 is the first monolithic jfet op amp to offer the low input voltage noise of an industry-standard bipolar op amp w ithout its inherent input current errors. this is demonstrated in figure 2, which compares input voltage noise versus input source resis- tance of the op27 and ad743 op amps. from this figure, it is clear that at high source impedance the low current noise of the ad743 also provides lower total noise. it is also important to note that with the ad743 this noise reduction extends all the way down to low source impedances. the lower dc current errors of the ad743 also reduce errors due to offset and drift at high source impedances (figure 3). 100 1k 10k 100k 1 10 100 1000 1m 10m source resistance ( ) op27 and resistor ad743 and resistor resistor noise only ad743 and resistor or op27 and resistor ( ) (? ? ?) ( ? ) r source r source o e in p u t v o lta g e n o is e (nv / h z ) figure 2. total input noise spectral density @ 1 khz vs. source resistance input offset voltage (mv) source resistance ( ) op27 ad743 100 10 1 0.1 100 1k 10k 100k 1m 10m figure 3. input offset voltage vs. source resistance designing circuits for low noise an op amp?s input voltage noise performance is typically di vided into two regions: flatband and low frequency noise. the ad743 offers excellent performance with respect to both. the figure of 2.9 nv/ hz @ 10 khz is excellent for a jfet input amplifier. the 0.1 hz to 10 hz noise is typically 0.38 v p-p. the user should pay careful attention to several design details in order to opti mize low frequency noise performance. random air currents can gen- erate varying thermocouple voltages that appear as low frequency noise; therefore, sensitive circuitry should be well shielded from air flow. keeping absolute chip temperature low also reduces low frequency noise in two ways. first, the low frequency noise is strongly dependent on the ambient temperature and increases above +25 c. second, since the gradient of temperature from the ic package to ambient is greater, the noise generated by random air currents, as previously mentioned, will be larger in magnitude. chip temperature can be reduced both by operation at reduced supply voltages and by the use of a suitable clip-on heat sink, if possible. low frequency current noise can be computed from the magni- tude of the dc bias current ? iqif nb = 2 and increases below approximately 100 hz with a 1/f power spectral density. for the ad743, the typical value of current noise is 6.9 fa/ hz at 1 khz. using the formula ? / iktrf n = 4 to compute the johnson noise of a resistor, expressed as a cur rent, one can see that the current noise of the ad743 is equivalent to that of a 3.45 qcv i dq dt == and as shown, voltage, current, and charge noise can all be directly related. the change in open circuit voltage ( v) on a capacitor will equal the combination of the change in charge ( q/c) and the change in capacitance with a built in charge (q/ c).
rev. e e8e ad743 figures 4 and 5 show two ways to buffer and amplify the output of a charge output transducer. both require using an amplifier that has a very high input impedance, such as the ad743. figure 4 shows a model of a charge amplifier circuit. here, amplifica- tion depends on the principle of conservation of charge at the input of amplifier a1, which requires that the charge on ca paci- tor c s be transferred to capacitor c f , thus yielding an output voltage of q/c f . the amplifier?s input voltage noise will appear at the output amplified by the noise gain (1 + (c s /c f )) of the circuit. a1 * optional, see text c s c f c b * r b * r1 = c s c f r1 r2 r2 r b * figure 4. charge amplifier circuit a2 * optional, see text c s c b * r b * r1 r2 r b figure 5. model for a high z follower with gain the circuit in figure 5 is simply a high impedance follower with gain. here the noise gain (1 + (r1/r2)) is the same as the gain from the transducer to the output. in both circuits, resistor r b is required as a dc bias current return. there are three important sources of noise in these circuits. amplifiers a1 and a2 contribute both voltage and current noise, while resistor r b contributes a current noise of nk t r f b = 4 where k = boltzman?s constant = 1.381 10 e23 joules/kelvin t = absolute temperature, kelvin (0 c = 273.2 kelvin) f = bandwidth?in hz (assuming an ideal brick wall filter) this must be root-sum-squared with the amplifier?s own current noise. figure 6 shows that these circuits in figures 4 and 5 have an identical frequency response and noise performance (provided that c s /c f = r1/ r2). one feature of the first circuit is that a t network is used to increase the effective resistance of r b and to improve the low frequency cutoff point by the same factor. ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 ?180 ?190 ?200 ?210 ?220 0.01 0.1 110 100 1k 10k 100 k frequency (hz) decibels referenced to 1v/ hz total output noise noise due to r b alone noise due to i b alone figure 6. noise at the outputs of the circuits of figures 4 and 5. gain = +10, c s = 3000 pf, r b = 22 m however, this does not change the noise contribution of r b which, in this example, dominates at low frequencies. the graph of figure 7 shows how to select an r b large enough to minimize this resistor?s contribution to overall circuit noise. when the equivalent current noise of r b (( 4kt)/r equals the noise of i b ( 2qi b b b b 4kt/r q 2qi t tr 4 k t 4q
rev. e ad743 e9e how chip package type and power dissipation affect input bias current as with all jfet input amplifiers, the input bias current of the ad743 is a direct function of device junction temperature, i b approximately doubling every 10 c. figure 8 shows the rela- tionship between the bias current and the junction temperature for the ad743. this graph shows that lowering the junction temperature will dramatically improve i b . ?60 ?40 ?20 0 20 40 60 80 100 120 140 10 ?12 10 ?11 10 ?10 10 ?9 10 ?8 10 ?7 10 ?6 input bias current (a) junction temperature ( c) t a = 25 c v s = 15v figure 8. input bias current vs. junction temperature the dc thermal properties of an ic can be closely approximated by using the simple model of figure 9, where current represents power dissipation, voltage represents temperature, and resistors represent thermal resistance (
rev. e e10e ad743 an input impedance compensated, sallen-key filter the simple high-pass filter of figure 13 has an important source of error which is often overlooked. even 5 pf of input capacitance in amplifier a will contribute an additional 1% of pass-band ampli- tude error, as well as distortion, proportional to the c/v characteristics of the input junction capacitance. the addition of the network designated z will balance the source impedance?as seen by a?and thus eliminate these errors. a 500k 500k 1000pf 1000pf +v s ?v s z 1000pf 1000pf 500k 500k z figure 13. input impedance compensated sallen-key filter two high performance accelerometer amplifiers two of the most popular charge-out transducers are hydro phones and accelerometers. precision accelerometers are typically cali- brated for a charge output (pc/ g ). * figures 14a and 14b show two ways in which to configure the ad743 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerom- eters. the input sensitivity of these circuits will be determined by the value of capacitor c 1 and is equal to v q c out out = 1 the ratio of capacitor c 1 to the internal capacitance ( c t ) of the transducer determines the noise gain of this circuit (1 + c t / c 1). the amplifier?s voltage noise will appear at its output amplified by this amount. the low frequency bandwidth of these circuits will be dependent on the value of resistor r 1. if a t network is used, the effective value is r 1(1 + r 2/ r 3). ad743 r2 9k r1 110m (5 22m ) output 0.8mv/pc * c1 1250pf r3 1k b and k model 4370 or equivalent * pc = picocoulombs g = earth?s gravitational constant figure 14a. basic accelerometer circuit ad743 r3 1k r2 9k r4 18m r1 110m (5 22m ) r5 18m output 0.8mv/pc c1 1250pf c3 2.2 f c2 2.2 f b and k model 4370 or equivalent ad711 figure 14b. accelerometer circuit using a dc servo amplifier a dc servo loop (figure 14b) can be used to assure a dc output which is <10 mv, without the need for a large compensating resistor when dealing with bias currents as large as 100 na. for optimal low frequency performance, the time constant of the servo loop ( r 4 c 2 = r 5 c 3) should be time cons r r r c tant +
10 1 1 2 3 1 low noise hydrophone amplifier hydrophones are usually calibrated in the voltage out mode. the circuits of figures 15a and 15b can be used to amplify the output of a typical hydrophone. figure 15a shows a typical dc-coupled circuit. the optional resistor and capacitor serve to counteract the dc offset caused by bias currents flowing through resistor r1. figure 15b, a variation of the original circuit, has a low frequency cutoff determined by an rc time constant equal to time cons t c c tan = 1 2 100 r2 1900 r4 * 10 8 r1 10 8 r3 100 output ad743 * optional, see text input sensitivity = ?179 db re. 1v/ pa ** ** 1v per micropascal b and k type 8100 hydrophone c t c1 * figure 15a. basic hydrophone amplifier
rev. e ad743 e11e r2 1900 r4 * r1 10 8 r3 100 output ad743 * optional, see text input sensitivity = ?179 db re. 1v/ pa ** ** 1v per micropascal b and k type 8100 hydrophone c t c c c1 * figure 15b. ac-coupled, low noise hydrophone amplifier r5 100k r1 10 8 r4 * 10 8 output dc output c c (100 ))) is the same as the circuit of figure 15a. the circuit of figure 15c uses a dc servo loop to keep the dc output at 0 v and to maintain full dynamic range for i b up to 100 na. the time constant of r7 and c2 should be larger than that of r1 and c t for a smooth low frequency response. the transducer shown has a source capacitance of 7500 pf. for smaller transducer capacitances ( 300 pf), the lowest noise can be achieved by adding a parallel rc network (r4 = r1, c1 = c t ) in series with the inverting input of the ad743. balancing source impedances as mentioned previously, it is good practice to balance the source impedances (both resistive and reactive) as seen by the inputs of the ad743. balancing the resistive components will optimize dc performance over temperature because balancing will mitigate the effects of any bias current errors. balancing input capacitance will minimize ac response errors due to the amplifier?s input capacitance and, as shown in figure 16, noise performance will be optimized. figure 17 shows the required external components for noninverting (a) and inverting (b) configurations. input capacitors (pf) rti voltage noise (nv/ hz ) 40 30 20 10 10 100 1000 unbalanced balanced 2.9nv/ hz figure 16. rti voltage noise vs. input capacitance output r1 r2 r b c b c s r s noninverting connection a a c b = c s r b = r s for r s >> r1 or r2 output r1 c s c f c b r s r b inverting connection b b c b = c f c s r b = r1 r s figure 17. optional external components for balancing source impedances
rev. e c00830e0e7/03(e) e12e ad743 outline dimensions revision history location page 7/03?data sheet changed from rev. d to rev. e. deleted k model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/02?data sheet changed from rev. c to rev. d. edits to product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 deleted ad7435 column from specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 deleted metallization photograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to reduce power supply operation for lower i b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 deleted 8-pin cerdip (q) package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8-lead plastic dual in-line package [pdip] (n-8) dimensions shown in inches and (millimeters) seating plane 0.180 (4.57) max 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 8 1 4 5 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.100 (2.54) bsc 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095aa 0.015 (0.38) min 16-lead standard small outline package [soic] wide body (r-16) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013aa seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 16 9 8 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 10.50 (0.4134) 10.10 (0.3976) 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10

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